1. Field of the Invention
The present invention relates to a semiconductor including a MOS (metal oxide semiconductor) field effect transistor, and method of manufacturing the same.
2. Description of the Background Art
For a MOS field effect transistor (MOS transistor), increase in drain current as a driving current is one of the ways of improving characteristic of this MOS transistor. Carrier mobility is one of the determinants of drain current. The carrier mobility is virtually controlled by a substrate material, and therefore, it can hardly be changed. On the other hand, it has been found that scattering probability and effective mass of carriers are altered by the change in lattice spacing of substrate atoms, allowing change of carrier mobility.
SiGe has wider lattice spacing than Si. In a substrate including SiGe and Si stacked thereon, the lattice spacing of the upper-layer Si is widened accordingly. The substrate including the widened lattice spacing of silicon is called as a “strained silicon substrate”. The strained silicon substrate has a higher carrier mobility than a conventional silicon substrate, providing increase in drain current of a MOS transistor formed thereon. An example of such conventional art is given in the non-patent document 1, Welser et al., “NMOS and PMOS Transistors Fabricated in Strained Silicon/Relaxed Silicon-Germanium Structures”, pp. 1000–1002, International Electron Device Meeting 1992, and in the non-patent document 2, T. Mizuno et al., “High Performance Strained-Si p-MOSFETs on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology”, pp. 934–936, International Electron Device Meeting 1999.
On the other hand, the strained silicon substrate encounters the problems as follows which result from use of SiGe as a substrate material: crystal defect and deterioration in surface roughness caused by SiGe, rise in substrate temperature due to low heat conductivity of SiGe, increase in short-channel effect in a p-channel MOS transistor covering band discontinuity at an interface between SiGe and Si, or the like. Other problems involved therein associated with process steps include inapplicability to STI (shallow trench isolation) technique, or insufficient activation annealing, for example. In view of this, for actually using the strained silicon substrate in LSIs, there remain a lot of problems to be solved.
By way of example, Japanese Patent Application Laid-Open No. 2002-93921 (pp. 3–6 and FIGS. 1–19), hereinafter referred to as the patent document 1, discloses that the lattice spacing of silicon of a MOS transistor may be varied by applying stress to a silicon substrate.
By way of example, tensile stress exerted on a channel region causes increase in driving current of an n-channel MOS transistor (nMOS transistor), while causing reduction in driving current of a p-channel MOS transistor (pMOS transistor). Conversely, compressive stress exerted on the channel region causes increase in driving current of the pMOS transistor, while causing reduction in driving current of the nMOS transistor.
As discussed, the strained silicon substrate including SiGe still faces the problems to be solved. Therefore, more simple way has been sought to improve characteristic of a MOS transistor.
According to the patent document 1, stress exerted to a gate electrode is applied to a channel region of a silicon substrate. As a result, channel characteristic of a MOS transistor is improved without the need of preparing a strained silicon substrate.
As discussed, tensile stress exerted on a channel region causes increase in driving current of an nMOS transistor, while causing reduction in driving current in a pMOS transistor. In contrast, compressive stress exerted on the channel region causes increase in driving current of the pMOS transistor, while causing reduction in driving current of the NMOS transistor. Therefore, stress to be exerted should differ at least between the NMOS and pMOS transistors.
It is thus required in the patent document 1 to employ different gate electrode materials and different deposition temperatures thereof between the NMOS and pMOS transistors. As a result, a gate electrode of the nMOS transistor and that of the pMOS transistor cannot be provided in the same process step, causing complication of the manufacturing steps.